Integer and floating point to binary converter

ABSTRACT

In a data processing system having a plurality of storage units, each unit therein storing in integer or normalized floating point format, an exponent sign bit, an exponent field, an integer/fraction sign bit, and an integer/fraction field, a converter transforms the stored data into pure binary values of selectively the same or the inverse relative order. To convert into the same relative order, the exponent sign bit is complemented if the integer/fraction sign bit is a logical zero and the exponent is complemented if otherwise. Thereafter, the integer/fraction bit is complemented. To convert into the inverse relative order, the exponent sign bit is complemented if the integer/fraction sign bit is a logical one and the exponent field is complemented if otherwise. Also, the integer/fraction field is complemented.

This is a division of application Ser. No. 605,251, filed Aug. 18, 1975,now U.S. Pat. No. 4,007,439.

BACKGROUND OF THE INVENTION

As speed requirements of computer systems have increased, systemsemploying greater numbers of parallel processors have been developed.One such system, has in the order of 64 parallel processors, see U.S.Pat. No. 3,537,074, issued Oct. 27, 1970 to R. A. Stokes et al, andassigned to the assignee of the present invention.

Present day large computer systems incorporating a high degree ofparallelism often include a plurality of widely scattered registers.When data in these registers are to be compared, the propagation delaysinvolved in transmitting data from each register to a central comparatorand back consumes precious processing time and limits the overallthroughput of the system.

Certain calculations in large parallel computer systems require thedetermination of which register(s) in a plurality of scattered registersare storing either the highest or lowest value numerical data.

When such numerical data is stored in either floating point or integerformat, determination of which register is storing either the highest orthe lowest data value requires complex parallel or time consuming serialdata comparison.

Conversion of all data to binary equivalents greatly eases thecomparison task but such comparison is in itself relatively complex andcostly in terms of hardware or firmware. Great simplification isachieved in the overall determination task by merely converting thestored data to a binary representation which maintains the same relativemagnitude ordering of the original stored data but not necessarily theexact binary equivalents thereof.

It is therefore an object of the present invention to provide aconverter to transform a plurality of floating point or integer valuesinto binary values of selectively the same or the inverse magnitudeordering.

It is a further object of the present invention to provide such aconverter capable of implementation with relatively inexpensivecomponents combined to function in a high speed efficient manner.

SUMMARY OF THE INVENTION

The above and other objects of the invention are realized by convertingstored floating point or integer data into binary data havingselectively either the same or the inverse relative magnitude ordering.The stored integer or floating point data includes an exponent sign bit,an exponent field, an integer/fraction sign bit, and an integer/fractionfield. To convert into the same relative order, the exponent sign bit iscomplemented if the integer/fraction sign bit is a logical zero and theexponent field is complemented if the otherwise. Also, theinteger/fraction bit is complemented. To convert into the relativeinverse relative order, the exponent sign bit is complemented if theinteger/fraction sign is a logical one and the exponent field iscomplemented if otherwise. Also, the integer/fraction field iscomplemented.-;

The system configuration and operational details given above have beenpresented in simplified form. Other features of the invention willbecome more fully apparent in the drawings and detailed descriptionpresented hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram showing the features of the presentinvention;

FIG. 2A presents the integer format used in the preferred embodiment ofthe invention;

FIG. 2B presents the floating point format used in the preferredembodiment of the invention;

FIG. 2C is a table demonstrating the two's complement normalizednumerical format used in the invention;

FIG. 3 is a logic diagram of a comparator shown in FIG. 1;

FIG. 4 is an alternate logic diagram for the comparator of FIG. 3;

FIG. 5 is a truth table for a decode circuit shown in FIG. 1;

FIG. 6 is a truth table for a compare circuit shown in FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

The integer and floating point converting method and apparatus of thepresent invention resides in a large parallel processing environmenthaving a plurality of processing elements, see FIG. 1. Each element 11includes an A register 13 for storing numerical data in normalizedfloating point or integer formats. Routinely, the A registers 13 storenumerical data temporarily before, during or after processing; i.e.,multiplication, division, addition, subtraction, etc. Occasionallyhowever, it becomes necessary to compare data in all the A registers 13to determine which A register(s) 13 is storing either the highest orlowest value numerical data. In accord with the present invention thedetermination process involves two basic steps wherein the numericaldata in each A register 13 is first converted into a pure binary patternand thereafter all binary patterns are searched two-bits-at-a-time todetermine which binary pattern(s) has selectively either the highest orthe lowest relative value.

Each A register 13 stores two's complement numerical data which may bein either integer, see FIG. 2A, or normalized floating point, see FIG.2B, format. In both integer and floating point format, a first bit 15,hereafter referred to as exponent sign bit 15, functions as the mostsignificant bit when viewing the format as a pure binary number. Theexponent sign bit 15 is always set to a logical zero in the integerformat and signifies the sign of the exponent in floating point formatwith a logical zero signifying a positive exponent and a logical onesignifying a negative exponent.

Immediately following the exponent sign bit 15 in both integer andfloating point formats is a first field of bits hereinafter referred toas the exponent field 17. In integer format all bits in the exponentfield 17 are set to logical zero. In floating point format the exponentfield 17 represents the value of the exponent, see FIG. 2C. The exponentfield 17 may comprise three bits as shown in FIG. 2C or more if requiredfor the numerical calculation range of a specific application orcomputer system. An exponent field 17 comprising seven bits has beenfound to be satisfactory for a wide range of applications.

Following the exponent field 17 is integer/fraction sign bit 19 whichrepresents the integer sign in integer format and fraction sign infloating point format. A logical zero integer/fraction sign bit 19signifies a positive integer or fraction whereas a logical oneinteger/fraction sign bit 19 signifies a negative integer or fraction.

A second field of bits 21 hereinafter referred to as theinteger/fraction field 21 follows the integer/fraction sign bit 19. Theinteger/fraction field 21 represents the integer value in integer formatand the fraction value in floating point format. The integer/fractionfield 21 may comprise three bits as shown in FIG. 2C or more if requiredfor the numerical calculation range of a specific application orcomputer system. An integer/fraction field 21 comprising 23 bits hasbeen found to be satisfactory for a wide range of applications.

The binary point 23 is considered to be following the integer/fractionfield 21 in integer format and preceding the integer/fraction field 21in floating point format.

As illustrated in FIG. 2C, the fraction portion of the floating pointformat is normalized. Thus, 0001 which represents a positive 1/8 valueis not valid. If +1/8 were thus permitted the eight bit representations0010 0001 and 0000 0100 both would have the value of +1/2. To assureonly one representation for each numerical value, the fraction isnormalized as shown in FIG. 2C by forbidding (or declaring invalid)fractions having their most significant bit the same logical value asthe integer/fraction sign bit 19. Likewise, to assure only onerepresentation for the numerical value "zero," the floating point "zero"is defined as the number having its exponent sign bit 15 at logical oneand all other bits at logical zero.

Referring again to FIG. 1, it is appreciated that the floating point orinteger representations discussed above are temporarily stored in aplurality of A registers 13 during the normal course of computercomputations. It matters not whether the numerical data is processedserially or in parallel into and out of the A registers 13. It isimportant that at a given period of time in the calculations a pluralityof A registers 13 are storing either integer or floating point data andthat it is desired to determine which A register(s) 13 is storing eitherthe highest or lowest value data. Such determination begins with dataconversion.

The numerical data in each A register 13 is fed in parallel through anassociated converter 25 to an associated B register 27 which serves tostore the converted numerical data. Each converter 25 operates under thecontrol of a select high/select low control unit 29 which generates alogical one or a logic zero depending on whether it is desired to searchfor the A register 13 storing the lowest or highest numerical data.Conversion differs for a high register search and a low register search.

To select the A register(s) 13 storing the highest value of numericaldata four conversion steps are followed. First, the exponent sign bit 15is complemented if the integer/fraction sign bit 19 is a logical zero.Second, the exponent field 17 is complemented if the integer/fractionsign bit 19 is a logical one. Third, the integer/fraction field 21remains unchanged. Finally, the integer/fraction sign bit 19 iscomplemented.

To select the A register(s) 13 storing the lowest value of numericalvalue another set of four conversion steps is followed. First, theexponent sign bit 15 is complemented if the integer/fraction sign bit 19is at a logical one. Second, the exponent field 17 is complemented ifthe integer/fraction sign bit 19 is at a logical zero. Third, theinteger/fraction field 21 is complemented. Finally, the integer/fractionsign bit 19 remains unchanged. The functions of converter 25 areimplemented using standard "off-the-shelf" hardware, see FIG. 3. Allbits of the integer/fraction field 21 and the integer/fraction sign bit19 are fed from the A register 13 to an integer/fraction complementcircuit 31 controlled by the select high/select low control unit 29. Alogical zero from the select high/select low control unit 29 to thecontrol input 33 of the integer/fraction complement circuit 31 willpermit all bits to pass therethrough unchanged to the appropriateconverted integer/fraction field 37 and integer/fraction sign bit 35portions of the B register 27. Conversely, a logical one from the selecthigh/select low control unit 29 will cause all bits to be complementedbefore passing to the B register 27.

The simple function of the integer/fraction complement circuit 31 may bephysically realized in many different ways well known to those skilledin the logic design art. As an example, many off-the-shelf addersavailable today also perform subtraction by complementing one input.Thus, if one input is held at logical zero, the other may be added to itor effectively passed through the adder unchanged. Likewise, with oneinput at zero, the subtraction function will serve to complement theother input. In a working model of the invention, a satisfactoryinteger/fraction complement circuit 31 has been fabricated using thearithmetic logic unit/function generator MC10181 available as a standarditem from Motorola, Inc. The MC10181 is only a four bit unit andtherefore parallel operation of two or more is required to handleinteger/fraction fields 21 containing more than three bits.

The converted integer/fraction sign bit output 36 of theinteger/fraction complement circuit 31 is logically inverted by astandard logic inverter 38 to produce an inverter output 39 which is thecomplement of the integer/fraction sign bit 19 when the integer/fractionfield 21 is not complemented and which is logically equal to theinteger/fraction sign bit 19 otherwise.

The exponent sign bit 15 of the A register 13 is applied to a firstinput 41 of an exclusive OR circuit 43. The second input 45 of theexclusive OR circuit 43 is fed to the output of an inverter 47 whichcomplements the integer/fraction sign bit 19 stored in A register 13.The output 49 of the exclusive OR circuit 43 is fed through an exponentcomplement circuit 51 and is outputted therefrom on data line 53 andstored as the converted exponent sign bit 55 in the B register 27.

The exponent complement circuit 51 operates under the control of theselect high/select low control circuit 29 to either pass bits throughunchanged or to complement same. As such the exponent complement circuit51 is identical to the integer/fraction complement circuit 31 and may bephysically realized as above described.

The exponent complement circuit 51 also serves to control thecomplementing of the exponent field 17 stored in A register 13. To thisend, all bits of the exponent field 17 are fed through data path 56 toan exclusive OR system 57. Another input 59 is provided to the exclusiveOR system 57 from the integer/fraction sign bit 19 stored in A register13. The exclusive OR system 57 functions as a plurality of exclusive ORcircuits, one for each bit in the exponent field 17 and may befabricated as a plurality of standard exclusive OR circuits. The output60 of the exclusive OR system 57 is fed through the exponent complementcircuit 51 into the converted exponent field 61 of B register 27.

As noted, the select high/select low control circuit 29 merely serves togenerate a logical one or a logical zero depending on whether a searchfor the high register(s) or low register(s) is desired. As such, thecontrol circuit 29 represents no more than a flip-flop output whoseinputs are generated by decision logic within the computer environmentin which the present invention is embodied.

FIG. 4 represents an alternative approach to the realization of theconverter 25. As compared to the converter 25 realization of FIG. 3, itis seen that the integer/fraction portions remain the same and that thedifferences involve the substitution of an exclusive OR circuit 63 forthe exponent complement circuit 51 and the slight rewiring necessitatedby the substitution. The exclusive OR 63 is inputted by theinteger/fraction sign bit 19 and the select high/select low controlcircuit 29. The exclusive OR circuit 63 drives the inverter 47 and theexclusive OR system 57. The output 60 of the exclusive OR system 57provides directly the converted exponent field 61. Following conversion,the process of searching for the high or low register commences, seeagain FIG. 1. As will be discussed in greater detail hereinafter, theconverted data in B register 27 is shifted two bits at a time into afirst and second input select circuit 67 and 69, respectively.Generally, the input circuits 67 and 69 merely pass bits from the Bregister 27 to the D flip-flop 71 and the E flip-flop 73, respectively.However, as will be discussed later, at the first step of a searchcycle, two bits are passed from the converter 25, one bit to the Dflip-flop 71 and the other bit to the E flip-flop 73.

The D output 75 of D flip-flop 71 and E output 77 of E flip-flop 73 areinputted to a decode circuit 79 having an A output 81, a B output 83,and a C output 85. FIG. 5 illustrates in truth table fashion thefunction of the decode circuit 79. It can be seen that the decodecircuit 79 provides basically a binary to 1 -in-3 conversion.

The A output 81 of decode circuit 79 feeds an OR circuit 87. As shown,the OR circuit 87 is fed by all A outputs 81, one for each element 11involved in the high/low register search. The output of OR circuit 87 isfed as the X input 89 of a compare circuit 91. As shown, there is onecompare circuit 91 for each element 11 involved in the search.

Likewise, the B output of decode circuit 79 feeds an OR circuit 93. Theoutput of OR circuit 93 is fed as the Y input 95 of the compare circuit91. Finally, the C output 85 of the decode circuit 79 feeds an ORcircuit 97. The output of OR circuit 97 is fed as the Z input 99 of thecompare circuit 91.

The function of the compare circuit 91 is illustrated in truth tablefashion in FIG. 6. As shown, the compare circuit 91 outputs a logicalzero on a reset line 101 (see FIG. 1) when the associated D output 75and E output 77 represent a binary number equal to or greater than anyother D output 75 and E output 77 generated by the other elements 11involved in the high/low register search.

A logical one on reset line 101 resets an element active flip-flop 103which in turn generates a logical level on line 105, which as will bedetailed hereinafter, effectively removes the associated element 11 fromthe high/low search.

The above procedure of examining data in the B registers 27 two bits ata time is continued under the control of shift control unit 107. Shiftcontrol unit 107 shifts bits out of the B register 27 two bits at a timefrom the most significant to the least significant bits. The shiftingprocedure is continued until all bits have been shifted out of the Bregister 27 and have been processed through the decode circuit 79, theOR circuits 87, 93 and 97, and the compare circuit 91. After all bitshave been shifted through the B register 27 only those elements 11having A registers 13 storing selectively either the highest or lowestvalue data remain active as indicated by the element activity flip-flop103.

The search procedure may be concluded early if only one element activityflip-flop 103 remains active at any point during the search. The elementactivity flip-flops 103 are monitored by element activity monitor 109.Element activity monitor 109 monitors all element activity flip-flops103 and generates an early search stop signal 111 when one and only oneelement activity flip-flop remains active. The element activity monitor109 may be fabricated from a counter which is decreased one count eachtime element activity flip-flop 103 indicates that its associatedelement 11 is no longer active and increased one count each time a newelement activity flip-flop 103 indicates that an element 11 has becomeactive. Alternative methods of physically realizing the element activitymonitor 109 may also be used. For example, the element activity monitor109 may be fabricated as an exclusive OR circuit which functions togenerate the early search/stop signal when one and only one elementactivity flip-flop 103 remains active.

The integer and floating point to binary converting system of thepresent invention has been described in a specific embodiment involvingthe search for a high data storing register or a low data storingregister. It is appreciated that other system configurations andapplications may be envisioned and implemented which are not beyond thescope of this invention. Further, although the present invention hasbeen described with a certain degree of particularity, it should beunderstood that the present disclosure has been made by way of exampleand that changes in the combination and arrangement of parts obvious toone skilled in the art, may be resorted to without departing from thescope and spirit of the invention.

What is claimed is:
 1. A converter for use in a logic element storing anumerical digital value having an exponent sign bit, an exponent field,an integer/fraction sign bit, and an integer/fraction field, saidconverter comprising:controller means having a first and a secondlogical state for controlling conversion of said numerical digitalvalue; means for complementing said exponent sign bit when both saidinteger/fraction sign bit equals a logical zero and said controllermeans is in said first logical state and when both said integer/fractionsign bit equals a logical one and said controller means is in saidsecond logical state; means for complementing said exponent field whenboth said integer/fraction sign bit equals a logical one and saidcontroller means is in said first logical state and when both saidinteger/fraction sign bit equals a logical zero and said controllermeans is in said second logical state; means for complementing saidinteger/fraction field when said controller means is in said secondlogical state; and means for complementing said integer/fraction bitwhen said controller means is in said first logical state.
 2. Aconverter for use in a logic element storing a numerical digital valuehaving an exponent sign bit, and an exponent field, an integer/fractionsign bit, and an integer/fraction field, said convertercomprising:exclusive OR means having an output for combining inexclusive OR fashion the exponent sign bit with the complement of theinteger/fraction sign bit and for like combining each bit individuallyof the exponent field with the integer/fraction sign bit and foroutputting all results of said combining; control means having a firstand a second logical state for controlling the conversion of saidnumerical digital value; complementing means coupled to the output ofsaid exclusive OR means, the integer/fraction sign bit, and theinteger/fraction field, said complementing means controlled by saidcontrol means for complementing each bit received when said controlmeans is in its first logical state and for passing uncomplemented eachbit received when said control means is in its second logical state. 3.A converter for use in a logic element storing a numerical digital valuehaving an exponent sign bit, an exponent field, an integer/fraction signbit, and an integer/fraction field, said converter comprising:controlmeans having a first and a second logical state for controllingconversion of said variable digital value; a first exclusive OR circuitfed by said control means and by the integer/fraction sign bit; a secondexclusive OR circuit fed by said first exclusive OR circuit and by eachbit of the exponent field whereby each bit in the exponent field iscombined in exclusive OR fashion with the output of said first exclusiveOR circuit; an inverter circuit complementing the output of said firstexclusive OR circuit; a third exclusive OR circuit fed by the exponentsign bit and by the output of said inverter circuit; and complementingmeans receiving the integer/fraction sign bit and each bit in theinteger/fraction field, said complementing means being controlled bysaid control means for complementing each bit received when saidcomplementing means is in its first logical state and for passinguncomplemented each bit received when said control means is in itssecond logical state.